http://blog.regehr.org/archives/793 Thu, 23 May 2013 17:10:41 +0000 hourly 1 http://wordpress.org/?v=3.5.1 http://blog.regehr.org/archives/793/comment-page-1#comment-5003 jilles Mon, 17 Sep 2012 23:08:09 +0000 http://blog.regehr.org/?p=793#comment-5003 Being able to combine a shift and an addition in one instruction is not that special. On x86, this can be done in a limited manner using LEA, which can multiply by 3, 5 and 9. This was also possible on the 68020 although it probably required additional move instructions there (because LEA requires address registers).

]]> http://blog.regehr.org/archives/793/comment-page-1#comment-4920 Mans Wed, 12 Sep 2012 19:29:56 +0000 http://blog.regehr.org/?p=793#comment-4920 It is quite common for RISC-type processors to lack hardware division. The usual explanation is that division is inherently iterative and doesn’t easily integrate into a classical RISC pipeline. The overhead of doing division in software is small enough in real-world code that it was generally made up for in simplified chip design. In modern CPU designs, the complexity has increased to the point where hardware division no longer constitutes a significant addition, and the latest version of the ARM architecture does include division instructions.

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